IEC 61188-1-2:1998 pdf download - Printed boards and printed board assemblies -Design and use - Part 1-2: Generic requirements -Controlled impedance

IEC 61188-1-2:1998 pdf download – Printed boards and printed board assemblies -Design and use – Part 1-2: Generic requirements -Controlled impedance

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IEC 61188-1-2:1998 pdf download – Printed boards and printed board assemblies -Design and use – Part 1-2: Generic requirements -Controlled impedance.
This part of IEC 61188 is intended to be used by circuit designers, packaging engineers. printed board manufacturers and procurement personnel so that all may have a common understanding of each area. The aim in packaging is to transfer a signal from one device to one or more other devices through a conductor. High-speed designs are defined as designs in which the interconnecting properties affect circuit performance and require unique considerations.
2 NormatIve references
The following normative documents contain provisions which, through reference In this text. constitute provisions of this part of IEC 61188. At the time of publication, the editions indicated were valid. All normative documents are subject to revision, and parties to agreements based on this part of IEC 61188 are encouraged to investigate the possibility of applying the most recent editions of the normative documents listed below. Members of IEC and ISO maintain registers of currently valid international standards.
IEC 61182 (all parts), Printed boards — Electronic data description and transfer
IEC 61182-1:1994 Printed boards — Electronic data description and transfer — Part 1: Printed board description in digital form
IEC 61189-3:1997, Test methods for electrical materials. inlerconnection structures and assemblies — Part 3: Test methods for Interconnection structures (printed boards)
3 EngIneering design overview
3.1 Device selectIon
Device technology options Include TTL. Schottky TTL. CMOS. ECL and GaAs. each with Its own set of power requirements, operating temperature range, density of chip, input impedance, output impedance, signal threshold levels, noise sensitivity, response time and output pulse risefall time, Many designs will have mixed technology where SMT and through hole packaging is intermixed with TTL. CMOS and ECL logic that may require multiple line widths (impedance values) on the same circuit layer or may compromise on a single conductor width that can provide enough margin for the different logic lamilies.
Chips can be individually mounted on a large board or assembled into small boards or multichip modules mounted onto large boards. Large systems may require several large board assemblies with another level of interconnection. Noise, timing, and signal degradation will accompany transitions from one packaging level to the next.
The electrical connections to the board can be of a variety of configurations ranging from pins that will in5ert through plated holes in the board, as in dual in-line packages. to a series of lands for surface mount devices. Requirements for component packaging are dependent on many factors including space, economics, electrical performance and reliability, as well as the predominant packaging styIG of the assembly. The components shall be provided in a style that is compatible with the assembly processes used to manufacture the printed board assembly.
The component package shall be considered when designing for high speed. In passive components the predominant factor will be the lead length as leads provide additional inductance and capacitance that will affect propagation speed and switching transients. To minimize these effects the leads may be as short as possible or removed. Surface mount devices can provide leadless packages which can be directly mounted to the interconnecting substrate.
NOTE — Component data iheets otten do not provide paras.hc values tor hii sp.ed noise and propagation speed consideratiOn,
Active devices, components such as integrated circuits, are often offered in several packages. In general, DIP packages, in either plastic or ceramic, have been the predominate package These are typically the largest packages and provide the poorest high speed operating environment due to lead configuration. The next best package style Is the surface mount package. These are offered in a variety of packages such as SOICs, PLCCs. PFQPS. TSOPs BGAs. These packages will typically reduce the lead capacitance and inductance.
To obtain the optimum performance from the device, the die can be directly mounted to the substrate using either the chip-on-board (COB), flip chip or tape automated bonding (TAB) approach. These offer an optimum approach since they minimize the lead capacitance’ inductance.

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